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參數(shù)資料
| 型號(hào)： | AT17LV65A-10JI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SRL CONFIG EEPROM 64K 20-PLCC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 可編程類型： | 串行 EEPROM |
| 存儲(chǔ)容量： | 64kb |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC |
| 包裝： | 管件 |
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6
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
4.10
READY
Open collector reset state indicator. Driven Low during power-on reset cycle, released when
power-up is complete. (recommended 4.7 k
pull-up on this pin if used).
4.11
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied
to V
CC.
4.12
V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
5.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17A Serial Configuration EEPROM has been
designed for compatibility with the Master Serial mode.
This document discusses the Altera FLEX FPGA device interfaces
6.
Control of Configuration
Most connections between the FPGA device and the AT17A Serial EEPROM are simple and
self-explanatory.
The DATA output of the AT17A series configurator drives DIN of the FPGA devices.
The master FPGA DCLK output or external clock source drives the DCLK input of the AT17A
series configurator.
The nCASC output of any AT17A series configurator drives the nCS input of the next
configurator in a cascaded chain of EEPROMs.
SER_EN must be connected to V
CC (except during ISP).
7.
Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the next clock signal to the configurator
asserts its nCASC output low and disables its DATA line driver. The second configurator recog-
nizes the low level on its nCS input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to a Low level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to a High level.
The
AT17LV65A devices do not have the nCASC feature to perform cascaded configurations.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AT17LV65A-10NC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10NI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10PI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10SC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
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