參數(shù)資料
型號(hào)： AT25HP512CI-10CI-2.7
元件分類： EEPROM
英文描述： EEPROM
中文描述： EEPROM的
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 219K
代理商： AT25HP512CI-10CI-2.7
8
AT25HP256/512
1113G
–
SEEPR
–
08/02
The AT25HP256/512 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25HP256/512 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
WRITE ENABLE (WREN):
The device will power up in the write disable state when V
CC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI):
To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR):
The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 1.
Instruction Set for the AT25HP256/512
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
Table 2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
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