參數(shù)資料
型號(hào)： AT25HP512W2-10SI-1.8
英文描述： SERIAL EEPROM|64KX8|CMOS|SOP|8PIN|PLASTIC
中文描述： 串行EEPROM的| 64KX8 |的CMOS |?？苵 8引腳|塑料
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 219K
代理商： AT25HP512W2-10SI-1.8
9
AT25HP256/512
1113G
–
SEEPR
–
08/02
WRITE STATUS REGISTER (WRSR):
The WRSR instruction allows the user to select
one of four levels of protection. The AT25HP256/512 is divided into four array seg-
ments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be READ only. The block
write protection levels and corresponding status register control bits are shown in Table
4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, t
WC
, RDSR).
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is
“
1
”
. Hardware write protection is
disabled when
either
the WP pin is high or the WPEN bit is
“
0.
”
When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE:
When the WPEN bit is hardware write protected, it cannot be changed back to
“
0
”
, as long as the WP pin is held low.
Table 3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write
cycle is in progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device
is not
WRITE ENABLED. Bit 1 = 1 indicates the
device is WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 5.
Bits 0-7 are 1s during an internal write cycle.
Table 4.
Block Write Protect Bits
Level
Status Register Bits
Array Addresses Protected
BP1
BP0
AT25HP256/512
0
0
0
None
1(1/4)
0
1
6000 - 7FFF/C000 - FFFF
2(1/2)
1
0
4000 - 7FFF/8000 - FFFF
3(All)
1
1
0000 - 7FFF/0000 - FFFF
Table 5.
WPEN Operation
WPEN
WP
WEN
ProtectedBlocks
UnprotectedBlocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
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