參數(shù)資料
型號(hào): AT32UC3A0512-CTUR
廠商: Atmel
文件頁(yè)數(shù): 92/97頁(yè)
文件大?。?/td> 0K
描述: IC MCU 512KB FLASH 144TFBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR®32 UC3 A0
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 109
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-TFBGA
包裝: 剪切帶 (CT)
其它名稱(chēng): AT32UC3A0512-CTURCT
2006 Microchip Technology Inc.
DS70119E-page 91
dsPIC30F6010
FIGURE 15-4:
DEAD-TIME TIMING DIAGRAM
15.8
Independent PWM Output
An independent PWM Output mode is required for driv-
ing certain types of loads. A particular PWM output pair
is in the Independent Output mode when the corre-
sponding PMOD bit in the PWMCON1 register is set.
No dead-time control is implemented between adjacent
PWM I/O pins when the module is operating in the
Independent mode and both I/O pins are allowed to be
active simultaneously.
In the Independent mode, each duty cycle generator is
connected to both of the PWM I/O pins in an output
pair. By using the associated duty cycle register and
the appropriate bits in the OVDCON register, the user
may select the following signal output options for each
PWM I/O pin operating in the Independent mode:
I/O pin outputs PWM signal
I/O pin inactive
I/O pin active
15.9
Single Pulse PWM Operation
The PWM module produces single pulse outputs when
the PTCON control bits PTMOD<1:0> = 10. Only edge-
aligned outputs may be produced in the Single Pulse
mode. In Single Pulse mode, the PWM I/O pin(s) are
driven to the active state when the PTEN bit is set.
When a match with a duty cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR reg-
ister is cleared, all active PWM I/O pins are driven to
the inactive state, the PTEN bit is cleared, and an
interrupt is generated.
15.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains eight
bits, POVDxH<4:1> and POVDxL<4:1>, that determine
which PWM I/O pins will be overridden. The lower half
of
the
OVDCON
register
contains
eight
bits,
POUTxH<4:1> and POUTxL<4:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
15.10.1
COMPLEMENTARY OUTPUT MODE
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead-time insertion is still performed when PWM
channels are overridden manually.
15.10.2
OVERRIDE SYNCHRONIZATION
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
Edge-Aligned mode, when PTMR is zero.
Center-Aligned modes, when PTMR is zero and
when the value of PTMR matches PTPER.
Duty Cycle Generator
PWMxH
PWMxL
Time selected by DTSxA bit (A or B)
Time selected by DTSxI bit (A or B)
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