參數(shù)資料
型號(hào): AT32UC3A1128-AUT
廠商: Atmel
文件頁(yè)數(shù): 71/97頁(yè)
文件大?。?/td> 0K
描述: IC MCU AVR32 128KB FLASH 100TQFP
產(chǎn)品培訓(xùn)模塊: AVR UC3 Audio Application
MCU Product Line Introduction
AVR EVK1105 Digital Audio Gateway Kit
AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 450
系列: AVR®32 UC3 A1
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: 以太網(wǎng),I²C,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 69
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
配用: ATSTK600-RC28-ND - STK600 ROUTING CARD AVR
ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATSTK600-TQFP100-ND - STK600 SOCKET/ADAPTER 100-TQFP
ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
73
AT32UC3A
15.2
Rev. J
15.2.1
PWM
1.
PWM channel interrupt enabling triggers an interrupt
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
2.
PWM counter restarts at 0x0001
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
3.
PWM update period to a 0 value does not work
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
15.2.2
ADC
1.
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
15.2.3
SPI
1.
SPI Slave / PDCA transfer: no TX UNDERRUN flag
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
2.
SPI FDIV option does not work
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
3.
SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and
NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
Fix/workaround
32058KS–AVR32–01/12
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