參數(shù)資料
型號: AT32UC3A464-C1UR
廠商: Atmel
文件頁數(shù): 13/94頁
文件大小: 0K
描述: IC MCU 64K FLASH 100VFBGA
產(chǎn)品培訓(xùn)模塊: AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR®32 UC3 A4
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-VFBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT32UC3A464-C1URDKR
20
32072SH–AVR32–10/2012
AT32UC3A3
3.5
Power Considerations
3.5.1
Power Supplies
The AT32UC3A3 has several types of power supply pins:
VDDIO: Powers I/O lines. Voltage is 3.3V nominal
VDDANA: Powers the ADC. Voltage is 3.3V nominal
VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal
VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the
core, memories, and peripherals. Voltage is 1.8V nominal
The ground pin GNDCORE is common to VDDCORE and VDDIN. The ground pin for VDDANA
is GNDANA. The ground pins for VDDIO are GNDIO.
Refer to Electrical Characteristics chapter for power consumption on the various supply pins.
3.5.2
Voltage Regulator
The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up
to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on
VDDCORE and powers the core, memories and peripherals.
Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid
oscillations.
The best way to achieve this is to use two capacitors in parallel between VDDCORE and
GNDCORE:
One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the
chip as possible.
One external 2.2F (or 3.3F) X7R capacitor (COUT2).
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop.
The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be
used in parallel (1nF NPO and 4.7F X7R).
For decoupling recommendations for VDDIO and VDDANA please refer to the Schematic
checklist.
3.3V
1.8V
VDDIN
VDDCORE
1.8V
Regulator
C
IN1
C
OUT1
C
OUT2
C
IN2
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