參數(shù)資料
型號: AT32UC3C2512C-A2UR
廠商: Atmel
文件頁數(shù): 110/110頁
文件大?。?/td> 0K
描述: IC MCU AVR32 512K FLASH 64TQFP
產(chǎn)品培訓模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 標準包裝
其它名稱: AT32UC3C2512C-A2URDKR
99
32117DS–AVR-01/12
AT32UC3C
4
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
10.1.7
TC
1
Channel chaining skips first pulse for upper channel
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
10.1.8
TWIM
1
SMBALERT bit may be set after reset
For TWIM0 and TWIM1 modules, the SMBus Alert (SMBALERT) bit in the Status Register
(SR) might be erroneously set after system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
For TWIM2 module, the SMBus Alert (SMBALERT) is not implemented but the bit in the Sta-
tus Register (SR) is erroneously set once TWIM2 is enabled.
Fix/Workaround
None.
10.1.9
TWIS
1
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
10.1.10
USBC
1
UPINRQx.INRQ field is limited to 8-bits
In Host mode, when using the UPINRQx.INRQ feature together with the multi-packet mode
to launch a finite number of packet among multi-packet, the multi-packet size (located in the
descriptor table) is limited to the UPINRQx.INRQ value multiply by the pipe size.
Fix/Workaround
UPINRQx.INRQ value shall be less than the number of configured multi-packet.
2
In USB host mode, downstream resume feature does not work (UHCON.RESUME=1).
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