參數(shù)資料
型號： AT40K40LV-3BQC
廠商： ATMEL CORP
元件分類： FPGA
英文描述： FPGA, 2304 CLBS, 40000 GATES, PQFP144
封裝： PLASTIC, TQFP-144
文件頁數(shù)： 66/67頁
文件大?。?/td> 1589K
代理商： AT40K40LV-3BQC
8
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Cell Connections
Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.
Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
Figure 4. Cell Connections
The Cell
Figure 5 depicts the AT40K/AT40KLV cell. Configuration bits for separate muxes and
pass gates are independent. All permutations of programmable muxes and pass gates
are legal. Vn (V1 -V5) is connected to the vertical local bus in plane n. Hn (H1 -H5)is
connected to the horizontal local bus in plane
n. A local/local turn in plane n is achieved
by turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let
signals into the cell from a local bus or to drive a signal out onto a local bus. Signals
coming into the logic cell on one local bus plane can be switched onto another plane by
opening two of the pass gates. This allows bus signals to switch planes to achieve
greater route ability. Up to five simultaneous local/local turns are possible.
The AT40K/AT40KLV FPGA core cell is a highly configurable logic block based around
two 3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT.
This means that any core cell can implement two functions of 3 inputs or one function of
4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-
stated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in
every cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an
important feature in the implementation of efficient array multipliers.
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40K/AT40KLV architecture well suited to
most digital design application areas, see Figure 6.
CELL
(a) Cell-to-cell Connections
(b) Cell-to-bus Connections
W
X
Y
Z
L
WXYZL
Orthogonal
Direct Connect
Diagonal
Direct Connect
Horizontal
Busing Plane
Vertical
Busing Plane
Plane 5
Plane 4
Plane 3
Plane 2
Plane 1
Plane
5
Plane
4
Plane
3
Plane
2
Plane
1
CELL
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PDF描述
AT40K40LV-3DQC FPGA, 2304 CLBS, 40000 GATES, PQFP208
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT40K40LV-3BQI 功能描述:IC FPGA 3.3V 2304 CELL 144TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3CGC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
AT40K40LV-3CQC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
AT40K40LV-3DQC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
AT40K40LV-3DQI 功能描述:IC FPGA 3.3V 2304 CELL 208PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
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