參數(shù)資料
型號: AT42QT1070-SSU
廠商: ATMEL CORP
元件分類: 速度傳感器和接近開關(guān)
英文描述: PROXIMITY SENSOR-CAPACITIVE, 0.6-2.6V, RECTANGULAR, SURFACE MOUNT
封裝: 0.150 INCH, ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14
文件頁數(shù): 7/38頁
文件大小: 509K
代理商: AT42QT1070-SSU
15
9596A–AT42–10/10
AT42QT1070
4.
I2C-compatible Communications (Comms Mode Only)
4.1
I2C-compatible Protocol
4.1.1
Protocol
The I2C-compatible protocol is based around access to an address table (see Table 5-1 on
page 18) and supports multibyte reads and writes. The maximum clock rate is 400 kHz.
See Section A on page 31 for an overview of I
2C-compatible bus operation.
4.1.2
Signals
The I
2C-compatible interface requires two signals to operate:
SDA - Serial Data
SCL - Serial Clock
A third line, CHANGE, is used to signal when the device has seen a change in the status byte:
CHANGE: Open-drain, active low when any capacitive key has changed state since the last
I
pulled up with an external resistor. If the status bytes change back to their original state
before the host has read the status bytes (for example, a touch followed by a release), the
CHANGE line is held low. In this case, a read to any memory location clears the CHANGE
line.
4.2
I2C-compatible Address
There is one preset I2C-compatible address of 0x1B. This is not changeable.
4.3
Data Read/Write
4.3.1
Writing Data to the Device
The sequence of events required to write data to the device is shown next.
1.
The host initiates the transfer by sending the START condition
2.
The host follows this by sending the slave address of the device together with the
WRITE bit.
Table 4-1.
Description of Write Data Bits
Key
Description
S
START condition
SLA+W
Slave address plus write bit
A
Acknowledge bit
MemAddress
Target memory address within device
Data
Data to be written
P
Stop condition
SLA+W
MemAddress
AA
S
Data
A
P
Host to Device
Device to Host
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