參數(shù)資料
型號： AT6003-4AI
廠商： Atmel
文件頁數(shù)： 12/28頁
文件大?。?/td> 0K
描述： IC FPGA 9K GATE 4NS 100VQFP
標準包裝： 90
系列： AT6000(LV)
邏輯元件/單元數(shù)： 1600
輸入/輸出數(shù)： 80
門數(shù)： 9000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
其它名稱： AT60034AI
AT6000(LV) Series
2
Devices range in size from 4,000 to 30,000 usable gates,
and 1024 to 6400 registers. Pin locations are consistent
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
AT6000 Series FPGAs utilize a reliable 0.6 m single-poly,
double-metal CMOS process and are 100% factory-tested.
Atmel's PC- and workstation-based Integrated Develop-
ment System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architecture was developed to provide the high-
est levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small size leads to arrays with large numbers of cells,
greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient commu-
nication over medium and long distances.
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array
of identical cells (Figure 1). The array is continuous and
completely uninterrupted from one edge to the other,
except fo r bus re pe at ers spaced every eight cells
(Figure 2).
In addition to logic and storage, cells can also be used as
wires to connect functions together over short distances
and are useful for routing in tight spaces.
The Busing Network
There are two kinds of buses: local and express (see
Figures 2 and 3).
Local buses are the link between the array of cells and the
busing network. There are two local buses – North-South 1
and 2 (NS1 and NS2) – for every column of cells, and two
local buses – East-West 1 and 2 (EW1 and EW2) – for
every row of cells. In a sector (an 8 x 8 array of cells
enclosed by repeaters) each local bus is connected to
every cell in its column or row, thus providing every cell in
the array with read/write access to two North-South and
two East-West buses.
Figure 1. Symmetrical Array Surrounded by I/O
相關PDF資料
PDF描述
AT6003-4AC IC FPGA 9K GATE 4NS 100VQFP
AT6003-2QI IC FPGA 2NS 132BQFP
AT6003-2QC IC FPGA 9K GATE 2NS 132BQFP
AT6003-2JI IC FPGA 2NS 84PLCC
AMC36DRXS-S734 CONN EDGECARD 72POS DIP .100 SLD
相關代理商/技術參數(shù)
參數(shù)描述
AT6003-4JC 功能描述:FPGA - 現(xiàn)場可編程門陣列 ASICS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-4JI 功能描述:FPGA - 現(xiàn)場可編程門陣列 9K GATE 4NS 84 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-4QC 功能描述:FPGA - 現(xiàn)場可編程門陣列 AT6K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003-4QI 功能描述:FPGA - 現(xiàn)場可編程門陣列 AT6K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
AT6003A-2AC 功能描述:FPGA - 現(xiàn)場可編程門陣列 9000 GATE - 2NS RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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