參數資料
| 型號： | AT6010H-4QC |
| 廠商： | Atmel |
| 文件頁數： | 2/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 4NS 240PQFP |
| 標準包裝： | 24 |
| 系列： | AT6000(LV) |
| 邏輯元件/單元數： | 6400 |
| 輸入/輸出數： | 204 |
| 門數： | 30000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 240-BFQFP |
| 供應商設備封裝： | 240-PQFP（32x32） |
| 其它名稱： | AT6010H4QC |
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AT6000(LV) Series
10
memory to configure the FPGA. Addresses change after
the rising edge of the CCLK signal.
CSOUT or I/O
When cascading devices, CSOUT is an output used to
enable other devices. CSOUT should be connected to the
CS input of the downstream device. The CSOUT function is
optional and can be disabled during initial programming
when cascading is not used. When cascading devices,
CSOUT should be dedicated to configuration and not used
as a configurable I/O.
CHECK or I/O
During configuration, CHECK is a TTL input that can be
used to enable the data check function at the beginning of
a configuration cycle. No data is written to the device while
CHECK is low. Instead, the configuration file being applied
to D0 (or D0 - D7, in parallel mode) is compared with the
current contents of the internal configuration RAM. If a mis-
match is detected between the data being loaded and the
data already in the RAM, the ERR pin goes low. The
CHECK function is optional and can be disabled during ini-
tial programming.
ERR or I/O
During configuration, ERR is an output. When the CHECK
function is activated and a mismatch is detected between
the current configuration data stream and the data already
loaded in the configuration RAM, ERR goes low. The ERR
ouput is a registered signal. Once a mismatch is found, the
signal is set and is only reset after the configuration cycle is
restarted. ERR is also asserted for configuration file errors.
The ERR function is optional and can be disabled during
initial programming.
Device Pinout Selection (Max. Number of User I/O)
AT6002
AT6003
AT6005
AT6010
84 PLCC
64 I/O
-
100 VQFP
80 I/O
-
132 PQFP
96 I/O
108 I/O
144 TQFP
95 I/O
120 I/O
108 I/O
120 I/O
208 PQFP
-
172 I/O
240 PQFP
-
204 I/O
Bit-stream Sizes
Mode(s)
Type
Beginning Sequence
AT6002
AT6003
AT6005
AT6010
1
Parallel
Preamble
2677
4153
8077
16393
2
Parallel
Preamble
2677
4153
8077
16393
3
Serial
Null Byte/Preamble
2678
4154
8078
16394
4
Serial
Null Byte/Preamble
2678
4154
8078
16394
5
Parallel
Preamble
2677
4153
8077
16393
6
Parallel
Preamble/Preamble
2678
4154
8078
16394
相關PDF資料 |
PDF描述 |
|---|---|
| IDT71V424S12YG8 | IC SRAM 4MBIT 12NS 36SOJ |
| AT6010H-2QI | IC FPGA 2NS 240PQFP |
| AT6010H-2QC | IC FPGA 2NS 240PQFP |
| IDT71V416S12YG8 | IC SRAM 4MBIT 12NS 44SOJ |
| AT6010A-4AI | IC FPGA 4NS 144TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AT6010H-4QI | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA 30K GATE 4NS IND TEMP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| AT6010HLV-4QC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT6010LV-4JC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT6010LV-4QC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Coprocessor Field Programmable Gate Arrays |
| AT60111 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | NPN | 8MA I(C) | SOT-143 |
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