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參數(shù)資料
| 型號(hào)： | AT80251G2D-SLSUM |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 11/77頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU ROMLESS 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 972 |
| 系列： | 8x251 |
| 核心處理器： | C251 |
| 芯體尺寸： | 8/16-位 |
| 速度： | 24MHz |
| 連通性： | EBI/EMI，I²C，Microwire，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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19
AT/TSC8x251G2D
4135F–8051–11/06
Table 12.
Configuration Byte 1
UCONFIG1
Notes: 1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI
instruction. INTR must be set if interrupts are used with code executing outside
region FF:.
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
7654
3210
CSIZE
-
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit
Number
Bit Mnemonic
Description
7
CSIZE
TSC87251G2D
On-Chip Code Memory Size bit(1)
Clear to select 16 KB of on-chip code memory (TSC87251G1D
product).
Set to select 32 KB of on-chip code memory (TSC87251G2D product).
TSC80251G2D
TSC83251G2D
Reserved
Set this bit when writing to UCONFIG1.
6-
Reserved
Set this bit when writing to UCONFIG1.
5-
Reserved
Set this bit when writing to UCONFIG1.
4INTR
Interrupt Mode bit(2)
Clear so that the interrupts push two bytes onto the stack (the two lower
bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes
of the PC register and the PSW1 register).
3WSB
Wait State B bit
(3)
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
2WSB1#
Wait State B bits
Select the number of wait states for RD#, WR# and PSEN# signals for
external memory accesses (only region 01:).
WSB1#
WSB0#
Number of Wait States
00
3
01
2
10
1
11
0
1WSB0#
0EMAP#
On-Chip Code Memory Map bit
Clear to map the upper 16 KB of on-chip code memory (at FF:4000h-
FF:7FFFh) to the data space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 KB of on-chip code memory (at FF:4000h-
FF:7FFFh) to the data space.
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