參數(shù)資料
型號: AT80C51RA2-RLTUM
廠商: Atmel
文件頁數(shù): 18/84頁
文件大小: 0K
描述: IC 8051 MCU ROMLESS 44VQFP
標(biāo)準(zhǔn)包裝: 800
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40/20MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
2007-2012 Microchip Technology Inc.
DS70292G-page 27
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.6
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
R/C-0
R-0
R/C-0
R -0
R/W-0
OA
OB
SA(1)
SB(1)
OAB
SAB(4)
DA
DC
bit 15
bit 8
R/W-0(3)
R-0
R/W-0
IPL<2:0>(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator (Sticky) Status bit(4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1.
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
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