參數(shù)資料
型號(hào): AT80C51RA2-SLSUL
廠商: Atmel
文件頁(yè)數(shù): 4/84頁(yè)
文件大小: 0K
描述: IC 8051 MCU ROMLESS 44PLCC
標(biāo)準(zhǔn)包裝: 972
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 30/20MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 14
2007-2012 Microchip Technology Inc.
FIGURE 1-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 BLOCK DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP
IC1, 2, 7, 8
I2C1
PORTA
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-bit ALU
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program Memory
Data Latch
Lite
ral
Dat
a
16
Data Latch
Address
Latch
16
X RAM
Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-5
CNx
UART1, 2
OC/
PWM1-4
DCI
Remappable
Pins
DMA
RAM
DMA
Controller
PORTC
SPI1, 2
ECAN1
DAC1
Comparator
2 Ch.
RTCC
PMP/
EPSP
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