參數(shù)資料
型號： AT87C58X2-3CSUL
廠商： Atmel
文件頁數(shù)： 28/62頁
文件大小： 0K
描述： IC 8051 MCU 32K EPROM 40DIP
標(biāo)準(zhǔn)包裝： 216
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 30/20MHz
連通性： UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： OTP
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
34
4431E–8051–04/06
AT/TS8xC54/8X2
14. Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
CC switch-on. A warm start reset occurs while VCC is still
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 14-1.). POF is set by hardware
when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
ing the user to determine the type of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading
POF bit will return indeterminate value.
Table 14-1.
PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
Description
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when V
CC rises from 0 to its nominal voltage. Can also be set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
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