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參數(shù)資料
| 型號(hào)： | AT87F51-24JC |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MICRO CTRL 24MHZ 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | 87F |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 24MHz |
| 連通性： | UART/USART |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 4KB（4K x 8） |
| 程序存儲(chǔ)器類型： | OTP 快速閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the table below:
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
essary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
Lock Bit Protection Modes
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
No program lock features.
2
P
U
MOVC instructions executed from external program memory are disabled from fetching code
bytes from internal memory, EA is sampled and latched on reset, and further programming of the
QuickFlash is disabled.
3
P
U
Same as mode 2, also verify is disabled.
4
P
Same as mode 3, also external execution is disabled.
Programming the QuickFlash
The AT87F51 is shipped with the on-chip QuickFlash mem-
ory array ready to be programmed. The programming inter-
face needs a high-voltage (12-volt) program enable signal
and is compatible with conventional third-party Flash or
EPROM programmers.
The AT87F51 code memory array is programmed byte-by-
byte.
Programming Algorithm: Before programming the
AT87F51, the address, data, and control signals should be
set up according to the QuickFlash programming mode
table and Figures 3 and 4. To program the AT87F51, take
the following steps:
1.
Input the desired memory location on the address
lines.
2.
Input the appropriate data byte on the data lines.
3.
Activate the correct combination of control signals.
4.
Raise EA/VPP to 12V.
5.
Pulse ALE/PROG once to program a byte in the Quick-
Flash array or the lock bits. The byte-write cycle is self-
timed and typically takes no more than 1.5 ms. Repeat
steps 1 through 5, changing the address and data for
the entire array or until the end of the object file is
reached.
Data Polling: The AT87F51 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written datum on PO.7. Once the write cycle
has been completed, true data are valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H, 031H, and 032H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 87H indicates 87F family
(032H) = 01H indicates 87F51
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| AT87F51-24JI | 功能描述:IC MICRO CTRL 24MHZ 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87F 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT87F51-24PC | 功能描述:8位微控制器 -MCU RO 556-AT89S51-24PC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT87F51-24PI | 功能描述:IC MICRO CTRL 24MHZ 40DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87F 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT87F51RC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AT87F51RC [Updated 2/00. 25 Pages] |
| AT87F51RC-24AC | 功能描述:IC MCU 8BIT 32KB FLASH 44TQFP 制造商:microchip technology 系列:87F 包裝:托盤 零件狀態(tài):停產(chǎn) 核心處理器:8051 核心尺寸:8-位 速度:24MHz 連接性:UART/USART 外設(shè):WDT I/O 數(shù):32 程序存儲(chǔ)容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP 快速閃存 EEPROM 容量:- RAM 容量:512 x 8 電壓 - 電源（Vcc/Vdd）:4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器類型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:44-TQFP 供應(yīng)商器件封裝:44-TQFP（10x10） 基本零件編號(hào):AT87F51RC 標(biāo)準(zhǔn)包裝:160 |
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