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參數(shù)資料
| 型號： | AT89C51ED2-SMSUM |
| 廠商： | Atmel |
| 文件頁數(shù)： | 103/137頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 64K 68PLCC |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 304 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 60MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 50 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-PLCC |
| 包裝： | 管件 |
| 配用： | AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU |
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68
4235K–8051–05/08
AT89C51RD2/ED2
16.3.3.1
Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-
master conflict for system control. In this case, the SPI system is affected in the following ways:
An SPI receiver/error CPU interrupt request is generated
The SPEN bit in SPCON is cleared. This disables the SPI
The MSTR bit in SPCON is cleared
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the
SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master device is
pulled low, there is no way that another Master attempts to drive the network. In this case, to
prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register
and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
16.3.3.2
Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done
during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an
access to SPDAT.
16.3.3.3
Overrun Condition
An overrun condition occurs when the Master device tries to send several data Bytes and the
Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this
case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the
SPDAT returns this Byte. All others Bytes are lost.
This condition is not detected by the SPI peripheral.
16.3.3.4
SS Error Flag (SSERR)
A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data
in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit
(reset of the SPI state machine).
16.3.4
Interrupts
Two SPI status flags can generate a CPU interrupt requests:
Table 16-2.
SPI Interrupts
Flag
Request
SPIF (SP data transfer)
SPI Transmitter Interrupt request
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
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