參數(shù)資料
型號: AT89C51IC2-RLRIM
廠商: Atmel
文件頁數(shù): 139/140頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8051 32K 5V 44-VQFP
標準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 剪切帶 (CT)
其它名稱: AT89C51IC2RLRIMCT
98
AT89C51IC2
4301D–8051–02/08
Table 72.
Miscellaneous status
C0h
Data byte in SSDAT has been
transmitted; NOT ACK has
been received
No SSDAT action or
No SSDAT action
0
1
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be transmitted
when the bus becomes free
C8h
Last data byte in SSDAT has
been transmitted (AA=0); ACK
has been received
No SSDAT action or
No SSDAT action
0
1
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be transmitted
when the bus becomes free
Status
Code
(SSCS)
Status of the 2-wire bus and
2-wire hardware
Application Software Response
Next Action Taken By 2-wire Software
To/from SSDAT
To SSCON
STA
STO
SI
AA
Status
Code
(SSCS)
Status of the 2-wire
bus and 2-wire
hardware
Application Software Response
Next Action Taken By 2-wire
Software
To/from
SSDAT
To SSCON
STA
STO
SI
AA
F8h
No relevant state
information
available; SI= 0
No SSDAT
action
No SSCON action
Wait or proceed current transfer
00h
Bus error due to an
illegal START or
STOP condition
No SSDAT
action
0
1
0
X
Only the internal hardware is
affected, no STOP condition is
sent on the bus. In all cases,
the bus is released and STO is
reset.
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