參數(shù)資料
型號(hào)： AT89C51IC2-RLRUM
廠商： Atmel
文件頁數(shù)： 129/140頁
文件大?。?/td> 0K
描述： IC 8051 MCU 32K FLASH 44-VQFP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 1,500
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LQFP
包裝： 剪切帶 (CT)
其它名稱： AT89C51IC2-RLRUMCT
89
AT89C51IC2
4301D–8051–02/08
slave address followed by the data direction bit which must be at logic 1 (R) for SSLC to
operate in the slave transmitter mode. After its own slave address and the R bit have
been received, the serial interrupt flag is set and a valid status code can be read from
SSCS. This status code is used to vector to an interrupt service routine. The appropriate
action to be taken for each of these status code is detailed in Table 71. The slave trans-
mitter mode may also be entered if arbitration is lost while SSLC is in the master mode.
If the AA bit is reset during a transfer, SSLC will transmit the last byte of the transfer and
enter state C0h or C8h. SSLC is switched to the not addressed slave mode and will
ignore the master receiver if it continues the transfer. Thus the master receiver receives
all 1’s as serial data. While AA is reset, SSLC does not respond to its own slave
address. However, the 2-wire bus is still monitored and address recognition may be
resume at any time by setting AA. This means that the AA bit may be used to tempo-
rarily isolate SSLC from the 2-wire bus.
Miscellaneous States
There are two SSCS codes that do not correspond to a define SSLC hardware state
(Table 72 ). These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not set yet. This occurs between other states and when SSLC is not involved in a
serial transfer.
Status 00h indicates that a bus error has occurred during an SSLC serial transfer. A bus
error is caused when a START or a STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions happen during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To
recover from a bus error, the STO flag must be set and SI must be cleared. This causes
SSLC to enter the not addressed slave mode and to clear the STO flag (no other bits in
SSCON are affected). The SDA and SCL lines are released and no STOP condition is
transmitted.
Notes
SSLC interfaces to the external 2-wire bus via two port pins: SCL (serial clock line) and
SDA (serial data line). To avoid low level asserting on these lines when SSLC is
enabled, the output latches of SDA and SLC must be set to logic 1.
Table 67. Bit frequency configuration
Bit Frequency ( kHz)
CR2
CR1
CR0
F
OSCA= 12 MHz
F
OSCA = 16 MHz
F
OSCA divided by
0
47
62.5
256
0
1
53.5
71.5
224
0
1
0
62.5
83
192
0
1
75
100
160
1
0
-
Unused
1
0
1
100
133.3
120
1
0
200
266.6
60
1
0.5 <. < 62.5
0.67 <. < 83
96 (256 - reload valueTimer 1)
(reload value range: 0-254 in mode 2)
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