參數(shù)資料
型號: AT89C51IC2-SLRIM
廠商: Atmel
文件頁數(shù): 15/140頁
文件大小: 0K
描述: IC MCU FLASH 8051 32K 5V 44-PLCC
標準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 剪切帶 (CT)
其它名稱: AT89C51IC2SLRIMCT
111
AT89C51IC2
4301D–8051–02/08
Table 88. Program Lock Bits of the SSB
Note:
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: don’t care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Flash Memory Status
AT89C51IC2 parts are delivered in standard with the ISP boot in the Flash memory.
After ISP or parallel programming, the possible contents of the Flash memory are sum-
marized on Figure 42.
Figure 42. Flash Memory Possible Contents
Memory Organization
In the AT89C51IC2, the lowest 32K of the 64 KB program memory address space is
filled by internal Flash.
When the EA pin is high, the processor fetches instructions from internal program Flash.
Bus expansion for accessing program memory from 32K upward automatic since exter-
nal instruction fetches occur automatically when the program counter exceeds 7FFFh
(32K). If the EA pin is tied low, all program memory fetches are from external memory.
Program Lock Bits
Protection Description
Security
level
LB0
LB1
1
U
No program lock features enabled.
2
P
U
ISP programming of the Flash is disabled.
3
X
P
Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
Default
After ISP
After Parallel
Programming
After Parallel
Programming
Application
Virgin
After ISP
or
Dedicated
ISP
Dedicated
ISP
7FFFh
Application
Virgin
or
Application
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