參數(shù)資料
型號(hào): AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 17/160頁
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
5-21
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
PLL2_X2FBD2:
These 6 register bits set the first feedback divider bits for
PLL2. On power-on-reset the value is set to 11000b (24
decimal).
Note: The value in the register is the actual coefficient minus one.
PLL2_X1FBD1:
These 5 register bits set the second feedback divider bits
for PLL2. On power-on-reset the value is set to 11000b (24
decimal).
Note: The value in the register is the actual coefficient minus one.
PLL2_PS:
These two bits determine the final divide function on the
VCO clock signal in PLL2.
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset these bits are reset to 11b (3 decimal).
Note: This means that PLL2 FOUT is programmed to be 48,000,000 Hz on startup.
Note: The value in the register is the actual coefficient minus one.
PLL2_EN:
This bit enables PLL2. If set, PLL2 is enabled. If this bit is
zero, PLL2 is disabled. On power-on-reset the value is set
to 0b.
nBYP2:
This bit selects the clock source for the processor clock
dividers. If set, PLL2 is the clock source. If this bit is set to
zero, the external clock is the clock source. On power-on-
reset, this bit defaults to 0b.
USBDIV:
These four bits set the divide ratio between the PLL2
output and the USB clock.
0000 - Divide by 1
1000 - Divide by 9
0001 - Divide by 2
1001 - Divide by 10
0010 - Divide by 3
1010 - Divide by 11
0011 - Divide by 4
1011 - Divide by 12
0100 - Divide by 5
1100 - Divide by 13
0101 - Divide by 6
1101 - Divide by 14
0110 - Divide by 7
1110 - Divide by 15
0111 - Divide by 8
1111 - Divide by 1
On power-on-reset these bits are reset to 0000b.
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