參數(shù)資料
型號(hào): AT89LP216-20XU
廠商: Atmel
文件頁數(shù): 17/98頁
文件大?。?/td> 0K
描述: MCU 8051 2K FLASH 20MHZ 16-TSSOP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 90
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 2KB(2K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
24
3621E–MICRO–11/10
AT89LP216
13.1.2
Input-only Mode
The input only port configuration is shown in Figure 13-2. The output drivers are tristated. The
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Input pins can be
safely driven to 5.5V even when operating at lower V
CC levels; however, the input threshold of
the Schmitt trigger will be set by the V
CC level and must be taken into consideration.
Figure 13-2. Input Only
Figure 13-3. Input Only for P1.3, P3.2 and P3.3
13.1.3
Open-drain Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to V
CC. The pull-
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in Figure 13-4.The input circuitry of P1.3, P3.2 and P3.3 is not disabled during
Power-down (see Figure 13-3). Open-drain pins can be safely pulled high to 5.5V even when
operating at lower V
CC levels; however, the input threshold of the Schmitt trigger will be set by
the V
CC level and must be taken into consideration.
Figure 13-4. Open-drain Output
13.1.4
Push-pull Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. Note that due to the 5V tolerant architecture, the push-pull output will have
reduced output high levels at DC operation and hot temperature. Under AC operation an inte-
grated boost circuit provides more source current. The push-pull port configuration is shown in
Figure 13-5. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see
Port
Pin
Input
Data
PWD
Port
Pin
Input
Data
Port
Pin
From Port
Register
Input
Data
PWD
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AT89LP216-20PU MCU 8051 2K FLASH 20MHZ 16-PDIP
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