參數(shù)資料
型號: AT89LP4052-16PI
廠商: Atmel
文件頁數(shù): 13/94頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 4K 20DIP
標(biāo)準(zhǔn)包裝: 18
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
其它名稱: AT89LP4052-20PI
AT89LP4052-20PI-ND
20
3547J–MICRO–10/09
AT89LP2052/LP4052
15. I/O Ports
All 15 port pins on the AT89LP2052/LP4052 may be configured to one of four modes: quasi-bidi-
rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port
modes may be assigned in software on a pin-by-pin basis as shown in Table 15-1. All port pins
default to input-only mode after reset. Each port pin also has a Schmitt-triggered input for
improved input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled
with the exception of P3.2 and P3.3, which may be used to wake-up the device. Therefore P3.2
and P3.3 should not be left floating during Power-down.
15.1
Quasi-bidirectional Output
Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-
bidirectional port can be used both as an input and output without the need to reconfigure the
port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an
external device to pull the pin low. When the pin is driven low, it is driven strongly and able to
sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port register for
the pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the
pin high if it is left floating.
Table 14-4.
IPH
– Interrupt Priority High Register
IPH = B7H
Reset Value = X0X0 0000B
Not Bit Addressable
PCH
PSH
PT1H
PX1H
PT0H
PX0H
Bit
7
6
543
21
0
Symbol
Function
PCH
Comparator Interrupt Priority High
PSH
Serial Port Interrupt Priority High
PT1H
Timer 1 Interrupt Priority High
PX1H
External Interrupt 1 Priority High
PT0H
Timer 0 Interrupt Priority High
PX0H
External Interrupt 0 Priority High
Table 15-1.
Configuration Modes for Port x, Bit y
PxM0.y
PxM1.y
Port Mode
0
Quasi-bidirectional
0
1
Push-pull Output
1
0
Input Only (High Impedance)
1
Open-Drain Output
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