參數(shù)資料
型號(hào): AT89LP52-20MU
廠商: Atmel
文件頁(yè)數(shù): 48/117頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8051 8K FLASH SPI 44VQFN
標(biāo)準(zhǔn)包裝: 360
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 托盤
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36
3709D–MICRO–12/11
AT89LP51/52
8.2.1
Interrupt Recovery from Power-down
Two external interrupt sources may be configured to terminate Power-down mode: external
interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0 or INT1, that inter-
rupt must be enabled by setting EX0 or EX1 in IE and must be configured for level-sensitive
operation by clearing IT0 or IT1.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is one, the wake-up period is internally timed as shown in Figure 8-1. At
the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 7-1 on page 33).
The interrupt pin need not remain low for the entire time-out period.
Figure 8-1.
Interrupt Recovery from Power-down (PWDEX = 1)
When PWDEX = “0”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure 8-
2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 8-2.
Interrupt Recovery from Power-down (PWDEX = 0)
8.2.2
Reset Recovery from Power-down
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in Figure 8-3. The internal clock will not be allowed to
propagate to the CPU until after the timer has timed out. The time-out period is controlled by the
Start-up Timer Fuses. (See Table 7-1 on page 33). If RST returns low before the time-out, a two
clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will
remain in reset until RST is brought low.
PWD
INT1
XTAL1
tSUT
Internal
Clock
PWD
INT1
XTAL1
Internal
Clock
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AT89LP52-20PU 功能描述:8位微控制器 -MCU Single-Cycle 8051 8K ISP Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP6440-20AU 功能描述:8位微控制器 -MCU Single-Cycle 8051 64K ISP Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP6440-20JU 功能描述:8位微控制器 -MCU Single-Cycle 8051 64K ISP Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP6440-20MU 功能描述:8位微控制器 -MCU Single-Cycle 8051 64K ISP Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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