參數(shù)資料
型號: AT89LS51-16PI
廠商: Atmel
文件頁數(shù): 31/31頁
文件大小: 0K
描述: IC 8051 MCU FLASH 4K 40DIP
標(biāo)準包裝: 9
系列: 89LS
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: UART/USART
外圍設(shè)備: WDT
輸入/輸出數(shù): 32
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 4 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
9
3053C–MICRO–6/08
AT89LS51
6.
Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
6.1
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89LS51, if EA is connected to V
CC, program fetches to addresses 0000H through
FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are
directed to external memory.
6.2
Data Memory
The AT89LS51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.
7.
Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
Table 5-3.
AUXR1: Auxiliary Register 1
AUXR1
Address = A2H
Reset Value = XXXXXXX0B
Not Bit
Addressable
––
DPS
Bit
7
6
5
4
3
2
1
0
Reserved for future expansion
DPS
Data Pointer Register Select
DPS
0
Selects DPTR Registers DP0L, DP0H
1
Selects DPTR Registers DP1L, DP1H
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