參數(shù)資料
型號: AT89LS52-16AU
廠商: Atmel
文件頁數(shù): 4/39頁
文件大?。?/td> 0K
描述: IC MCU 8K FLASH 16MHZ 44-TQFP
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 160
系列: 89LS
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: UART/USART
外圍設備: WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 4 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
12
2601C–MICRO–06/08
AT89LS52
8.
UART
The UART in the AT89LS52 operates the same way as the UART in the AT89C51 and
AT89C52. For further information on the UART operation, please click on the document link
below:
9.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89LS52 operate the same way as Timer 0 and Timer 1 in the
AT89C51 and AT89C52. For further information on the timers’ operation, please click on the
document link below:
10. Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 5-2). Timer 2 has
three operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON, as shown in Table 5-2. Timer 2 consists of two 8-bit
registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-
lator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since two machine cycles (24 oscillator
periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the
oscillator frequency. To ensure that a given level is sampled at least once before it changes, the
level should be held for at least one full machine cycle.
Table 10-1.
Timer 2 Operating Modes
RCLK +TCLK
CP/RL2
TR2
MODE
0
1
16-bit Auto-reload
0
1
16-bit Capture
1
X
1
Baud Rate Generator
X
0
(Off)
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