參數(shù)資料
型號(hào): AT89S8253-24AC
廠商: Atmel
文件頁數(shù): 3/60頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 12K 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: 89S
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 12KB(12K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-TQFP
包裝: 托盤
11
3286P–MICRO–3/10
AT89S8253
7.
Power-On Reset
A Power-On Reset (POR) is generated by an on-chip detection circuit. The detection level is
nominally 1.4V. The POR is activated whenever V
CC is below the detection level. The POR cir-
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on.
When V
CC reaches the Power-on Reset threshold voltage, the POR delay counter determines
how long the device is kept in POR after V
CC rise, nominally 2 ms. The POR signal is activated
again, without any delay, when V
CC falls below the POR threshold level. A Power-On Reset (i.e.
a cold reset) will set the POF flag in PCON.
Figure 7-1.
Power-up and Brown-out Detection Sequence
7.1
Memory Brown-out Protection
The AT89S8253 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
CC level
during operation by comparing it to a fixed trigger level of nominally 2.2V (2.4V max). The pur-
pose of the BOD is to ensure that if V
CC fails or dips, the Flash or EEPROM memories cannot be
erased/written at voltages too low for programming. At powerup the V
CC level must pass the
BOD threshold before execution starts. When V
CC decreases to a value below the trigger level,
the WRTINH bit in EECON is activated and futher programming of the Flash/EEPROM is
restricted. When V
CC increases above the trigger level, the BOD delay counter blocks program-
ming until after the timeout period has expired in approximately 2 ms. The BOD does not reset
the system as shown in Figure 7-1. To protect the system from errors induced by incorrect exe-
cution at lower voltages an external BOD circuit may be required.
POR
POR Level 1.4V
BOD Level 2.3V
Min V
CC Level 2.7V
XTAL1
WRTINH
Internal
RESET
t
V
CC
t
POR
(2 ms)
t
POR
(2 ms)
2.4V
1.2V
0
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