參數(shù)資料
型號(hào): AT89S8253-24PI
廠商: Atmel
文件頁數(shù): 31/60頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 12K 40DIP
標(biāo)準(zhǔn)包裝: 10
系列: 89S
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 12KB(12K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
37
3286P–MICRO–3/10
AT89S8253
20. Programming the Flash and EEPROM
Atmel’s AT89S8253 Flash microcontroller offers 12K bytes of In-System reprogrammable Flash
code memory and 2K bytes of EEPROM data memory.
The AT89S8253 is normally shipped with the on-chip Flash code and EEPROM data memory
arrays in the erased state (i.e. contents = FFH) and ready to be programmed. This device sup-
ports a parallel programming mode and a serial programming mode. The serial programming
mode provides a convenient way to reprogram the AT89S8253 inside the user’s system. The
parallel programming mode is compatible with conventional third-party Flash or EPROM
programmers.
The code and data memory arrays are mapped via separate address spaces in the parallel and
serial programming modes: 0000H to 2FFFH for code memory and 000H to 7FFH for data
memory.
The code and data memory arrays in the AT89S8253 are programmed byte-by-byte or by page
in either programming mode. To reprogram any non-blank byte in the parallel or serial mode, the
user needs to invoke the Chip Erase operation first to erase both arrays since there is no built-in
auto-erase capability.
Parallel Programming Algorithm: To program and verify the AT89S8253 in the parallel pro-
gramming mode, the following sequence is recommended (see Figure 26-1):
1.
Power-up sequence:
a.
Apply power between V
CC and GND pins.
b.
Set RST pin to “H”.
c.
Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 ms.
2.
Set PSEN pin to “L”
a.
ALE pin to “H”
b.
EA pin to “H” and all other pins to “H”.
3.
Raise EA/VPP to 12V to enable Flash programming, erase or verification. Enable the
P3.0 pull-up (10 K
Ω typical) for RDY/BSY operation.
4.
Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5,
P3.6, P3.7 to select one of the programming operations shown in the Flash Program-
ming Modes table.
5.
Apply the desired byte address to pins P1.0 to P1.7 and P2.0 to P2.5.
a.
Apply data to pins P0.0 to P0.7 for write code operation.
6.
Pulse ALE/PROG once to load a byte in the code memory array, the data memory
array, or the lock bits.
7.
Repeat steps 5 and 6, changing the address and data for up to 64 bytes in the code
memory page or 32 bytes in the data memory (EEPROM) page. When loading a page
with individual bytes, the interval between consecutive byte loads should be no longer
than 150 s. Otherwise the device internally times out and assumes that the page load
sequence is completed, rejecting any further loads before the page programming
sequence has finished. This timing restriction also applies to Page Write of the 64-byte
User Row.
8.
After the last byte of the current page has been loaded, wait for 5 ms or monitor the
RDY/BUSY pin until it transitions high. The page write cycle is self-timed and typically
takes less than 5 ms.
9.
To verify the last byte of the page just programmed, bring pin P3.4 to “L” and read the
programmed data at pins P0.0 to P0.7.
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