參數(shù)資料
型號(hào): AT90S1200A-4SC
廠商: Atmel
文件頁數(shù): 7/71頁
文件大小: 0K
描述: MCU 1K FLASH 4MHZ LV 20-SOIC
標(biāo)準(zhǔn)包裝: 37
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 4MHz
連通性: SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 1KB(512 x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
15
AT90S1200
0838H–AVR–03/02
Figure 17. Watchdog Reset during Operation
Interrupt Handling
The AT90S1200 has two Interrupt Mask Control Registers: the GIMSK (General Inter-
rupt Mask Register) at I/O space address $3B and the TIMSK (Timer/Counter Interrupt
Mask Register) at I/O address $39.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-
bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag
bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
General Interrupt Mask
Register GIMSK
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S1200 and always reads as zero.
Bit
7
6
5
4
3
2
1
0
$3B
-
INT0
-
GIMSK
Read/Write
R
R/W
R
Initial Value
0
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