參數(shù)資料
型號(hào)： AT90S8515-8JC
廠商： Atmel
文件頁(yè)數(shù)： 76/112頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8K FLSH 8MHZ 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（4K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
66
AT90S8515
0841G–09/01
Port B as General Digital I/O
All eight pins in Port B have equal functionality when used as digital I/O pins.
PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin.
If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn
is configured as an input pin. If PORTBn is set (one) when the pin is configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the
PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock is not
active.
Note:
n: 7,6…0, pin number.
Alternate Functions of Port B
The alternate pin configuration is as follows:
SCK – Port B, Bit 7
SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB7 bit. See the description of the SPI port for further details.
MISO – Port B, Bit 6
MISO: Master data input, slave data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB6 bit. See the description of the SPI port for further details.
MOSI – Port B, Bit 5
MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB5 bit. See the description of the SPI port for further details.
SS – Port B, Bit 4
SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as
an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin
is driven low. When the SPI is enabled as a master, the data direction of this pin is con-
trolled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled
by the PORTB4 bit. See the description of the SPI port for further details.
AIN1 – Port B, Bit 3
AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is
cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared
[zero]), this pin also serves as the negative input of the On-chip Analog Comparator.
Table 21. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
Pull up
Comment
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PBn will source current if ext. pulled low.
1
0
Output
No
Push-pull Zero Output
1
Output
No
Push-pull One Output
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