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參數(shù)資料
| 型號： | AT90USB1287 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller |
| 中文描述： | 8位64/128K的ISP字節(jié)閃存和控制器的USB微控制器 |
| 文件頁數(shù)： | 71/132頁 |
| 文件大?。?/td> | 10886K |
| 代理商： | AT90USB1287 |
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276
8151H–AVR–02/11
ATmega128A
24.15 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description.
24.16 Register Description
24.16.1
OCDR - On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
24.16.2
MCUCSR - MCU Control and Status Register
The MCU Control and Status Register contains control bits for general MCU functions, and pro-
vides information on which reset source caused an MCU Reset.
Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit
is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the
JTAG interface, a timed sequence must be followed when changing this bit: The application soft-
ware must write this bit to the desired value twice within four cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Bit
7
6
5
4321
0
MSB/IDRD
LSB
OCDR
Read/Write
R/W
Initial Value
0
0000
0
Bit
7
65432
10
JTD
–
–JTRF
WDRF
BORF
EXTRF
PORF
MCUCSR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT90USB1287-16AU | 功能描述:8位微控制器 -MCU 128kB Flash 4kB EEPROM 48 I/O Pins RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT90USB1287-16AUR | 功能描述:8位微控制器 -MCU 128K Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT90USB1287-16ME | 制造商:Atmel Corporation 功能描述: |
| AT90USB1287-16MU | 功能描述:8位微控制器 -MCU 128kB Flash 4kB EEPROM 48 I/O Pins RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT90USB1287-64QFN | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT90USB1287 (AVR) 64 QFN device (2.7V VCC 5.5V) |
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