參數(shù)資料
型號(hào): AT90USB82-16MU
廠商: Atmel
文件頁數(shù): 4/38頁
文件大小: 0K
描述: IC AVR MCU 8K FLASH 32QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 2,450
系列: AVR® 90USB
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,PS/2,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VFQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁面: 611 (CN2011-ZH PDF)
配用: ATSTK600-TQFP32-ND - STK600 SOCKET/ADAPTER 32-TQFP
ATSTK526-ND - KIT STARTER FOR AT90USB82/162
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
12
7707F–AVR–11/10
AT90USB82/162
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x0100. The initial value of the stack pointer is the last address of the internal
SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by three when the return address is pushed onto the
Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by three when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
4.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Y-register
70
7
0
R29 (0x1D)
R28 (0x1C)
15
ZH
ZL
0
Z-register
70
7
0
R31 (0x1F)
R30 (0x1E)
Bit
1514
1312
11109
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
765
43
210
Read/Write
R/W
Initial Value
0
1
0
111
11
111
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