參數(shù)資料
型號: AT91FR40162SB-CU
廠商: Atmel
文件頁數(shù): 6/22頁
文件大小: 0K
描述: IC ARM MCU FLASH 1K 121BGA
標(biāo)準(zhǔn)包裝: 2,250
系列: AT91
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 75MHz
連通性: EBI/EMI,UART/USART
外圍設(shè)備: WDT
輸入/輸出數(shù): 32
程序存儲器容量: 2MB(1M x 16)
程序存儲器類型: 閃存
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 121-BGA
包裝: 托盤
14
6410BS–ATARM–12-Jan-10
AT91FR40162SB
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility, enabling
the reset operation to adapt to the application. When this input is at a logic high level, the mem-
ory is in its standard operating mode; a low level on this input halts the current memory
operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a program
cycle is in progress, an attempted read of the last word written will return the complement of the
written data on I/O7. An open-drain NBUSY output pin provides another method of detecting the
end of a program or erase cycle. This pin is pulled low while program and erase cycles are in
progress and is released at the completion of the cycle. A toggle bit feature provides a third
means of detecting the end of a program or erase cycle.
The Flash memory is divided into 39 sectors for erase operations. To further enhance device
flexibility, an Erase Suspend feature is offered. This feature puts the erase cycle on hold for an
indefinite period and allows the user to read data from, or to write data to, any other sector within
the same memory plane. There is no need to suspend an erase cycle if the data to be read is in
the other memory plane.
The device has the capability to protect data stored in any sector. Once the data protection for a
sector is enabled, the data in that sector cannot be changed while input levels lie between
ground and VDDIO.
Note: This data protection does not prevent read accesses of the Flash.
A 6-byte command sequence (Enter Single Pulse Program Mode) allows the device to be written
to directly, using single pulses on the write control lines. This mode (Single-pulse Programming)
is exited by powering down the device or by pulsing the NRSTF pin low for a defined duration
and then bringing it back to VDDIO.
The following hardware features protect against inadvertent programming of the Flash memory:
VDDIO Sense – if VDDIO is below a certain level, the program function is inhibited.
VDDIO Power-on Delay – once VDDIO has reached the VDDIO sense level, the device will
automatically time out a certain duration before programming.
Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles.
Noise Filter – pulses of less than a certain duration on the WE or CE inputs will not initiate a
program cycle.
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