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參數(shù)資料
| 型號： | AT91M40800-33AU-999 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT RISC 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | AT91 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 帶卷 (TR) |
9
1348FS–ATARM–13-Apr-06
AT91M40800
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any
standard PIO line.
7.6.3
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to
be redefined dynamically by the software, the AT91M40800 microcontroller uses a remap com-
mand that enables switching between the boot memory and the internal primary SRAM bank
addresses. The remap command is accessible through the EBI User Interface, by writing one in
RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if
access to the other external devices (connected to chip-selects 1 to 7) is required. The remap
operation can only be changed back by an internal reset or an NRST assertion.
7.6.4
Abort Control
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
7.6.5
External Bus Interface
The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0
0000. It generates the signals that control access to the external devices, and can be configured
from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte-, half-word- and word-
aligned accesses.
For each of these banks, the user can program:
Number of wait states
Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
Data bus-width (8-bit or 16-bit).
With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte
Access Select mode) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte
Write Access mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in the case of
single-clock cycle access.
Table 7-1.
Boot Mode Select
BMS
Boot Memory
1
External 8-bit memory on NCS0
0
External 16-bit memory on NCS0
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