參數(shù)資料
型號： AT91SAM9XE512-QU
廠商： Atmel
文件頁數(shù)： 9/159頁
文件大?。?/td> 0K
描述： MCU ARM9 512K FLASH 208-PQFP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 24
系列： SAM9XE
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 180MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSC，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 56K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-MQFP，208-PQFP
包裝： 托盤
配用： AT91SAM9XE-EK-ND - KIT EVAL FOR AT91SAM9XE
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
PIC16F62X
DS40300C-page 104
Preliminary
2003 Microchip Technology Inc.
FIGURE 14-16:
WATCHDOG TIMER BLOCK DIAGRAM
TABLE 14-10: SUMMARY OF WATCHDOG TIMER REGISTERS
14.9
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low, or hi-
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
DD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators, and V
REF should be disabled. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
DD or
V
SS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
IHMC).
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS
2007h
Config.
bits
LVP
BODEN
MCLRE
FOSC2
PWRTE
WDTE
FOSC1
FOSC0
uuuu uuuu
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend:
_ = Unimplemented location, read as “0”, + = Reserved for future use
Note
1: Shaded cells are not used by the Watchdog Timer.
Note
1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
From TMR0 Clock Source
Watchdog
Timer
WDT
Enable Bit
0
1
8
8 to 1 MUX
PS<2:0>
To TMR0
01
PSA
WDT
Timeout
PSA
M
U
X
MUX
3
WDT POSTSCALER/
TMR0 PRESCALER
Note:
It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
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