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參數(shù)資料
| 型號： | ATF1500A-10AC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 32 MACROCELL 10NS 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 100 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
ATF1500A(L)
4
ATF1500A(L) Macrocell
ATF1500A Macrocell
The ATF1500A macrocell is flexible enough to support
highly-complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod-
uct term select multiplexer, OR/XOR/CASCADE logic, a
flip-flop, output select and enable, and logic array inputs.
Product Terms and Select Mux
Each ATF1500A macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler that selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1500A macrocell’s OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be
routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with little small additional delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate T-type flip-flops.
Flip-flop
The ATF1500A’s flip-flop has very flexible data and control
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa-
rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.
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參數(shù)描述 |
|---|---|
| ATF1500A-10AI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 1500 Gate RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1500A-10AU | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL 5V 10NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1500A-10JC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL CMPTBLE w/F1500 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1500A-10JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 1502 Gate RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1500A-10JU | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL CMPTBLE w/F1500 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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