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參數(shù)資料
| 型號： | ATF1500A-15JI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 15NS 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 100 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
| 其它名稱： | ATF1500A15JI |
ATF1500A(L)
11
Power-up Reset
The ATF1500A’s registers are designed to reset during
power-up. At a point delayed slightly from V
CC crossing
V
RST, all registers will be reset to the low state. As a result,
the registered output state will always be low on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the fol-
lowing conditions are required:
1. The V
CC rise must be monotonic, from below 0.7 volt,
2. After reset occurs, all input and feedback setup times
must be met before driving the clock signal high, and
3. Signals from which clocks are derived must remain sta-
ble during t
PR.
Power-down Mode
The ATF1500A includes an optional pin-controlled power-
down feature. When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 10 mA. During
power-down, all output data and internal logic states are
latched and held. Therefore, all registered and combinato-
rial output data remain valid. Any outputs that were in a
high-Z state at the onset of power-down will remain at
high-Z. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indetermi-
nate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs
using the power-down pin may not use the PD pin logic
array input. However, all other PD pin macrocell resources
may still be used, including the buried feedback and fold-
back product term array inputs.
Register Preload
The ATF1500A’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with preload vectors is compiled. Once downloaded, the
JEDEC file preload sequence will be done automatically
when vectors are run by any approved programmers. The
preload mode is enabled by raising an input pin to a high
voltage level. Contact Atmel PLD Applications for PRE-
LOAD pin assignments, timing and voltage requirements.
Output Slew Rate Control
Each ATF1500A macrocell contains a configuration bit for
each I/O to control its output slew rate. This allows selected
data paths to operate at maximum throughput while reduc-
ing system noise from outputs that are not speed-critical.
Outputs default to slow edges, and may be individually set
to fast in the design file. Output transition times for outputs
configured as “slow” have a t
SSO delay adder.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1500A fuse patterns. Once programmed, fuse
verify and preload are prohibited. However, the 160-bit
User Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Parameter
Description
Typ
Max
Units
tPR
Power-up
Reset Time
210
s
VRST
Power-up
Reset
Voltage
3.8
4.5
V
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| ATF1500A-7AC | 功能描述:IC CPLD 7NS 44TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:ATF15xx 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| ATF1500A-7JC | 功能描述:IC CPLD 7NS 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:ATF15xx 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| ATF1500A-7JI | 制造商:Atmel Corporation 功能描述:CPLD ATF1500A 1K GATES 32 MCRCLLS 166.7MHZ 5V 44PLCC - Trays |
| ATF1500ABV | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500ABV-12AC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
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