參數(shù)資料
型號: ATF1502BE-5AX44
廠商: Atmel
文件頁數(shù): 18/24頁
文件大?。?/td> 0K
描述: IC CPLD 64MC 1.8V 44-TQFP
標準包裝: 160
系列: ATF15xx
可編程類型: 系統(tǒng)內可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 7.0ns
電壓電源 - 內部: 1.7 V ~ 1.9 V
宏單元數(shù): 32
輸入/輸出數(shù): 32
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
3
3492A–PLD–12/05
ATF1502BE
Figure 1-2.
Block Diagram
Each of the 32 macrocells generates a buried feedback signal that goes to the global bus (see
Figure 1-2). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1502BE allows fast, efficient generation of complex logic functions. The ATF1502BE con-
tains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1502BE macrocell, shown in Figure 1-3, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1502BE. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project name,
part number, revision or date. The User Signature is accessible regardless of the state of the
security fuse.
The ATF1502BE device is an In-System Programming (ISP) device. It uses the industry-stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan
Description Language (BSDL). ISP allows the device to be programmed without removing it from
the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design
modifications to be made in the field via software.
B
32
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