參數(shù)資料
型號(hào): ATF1504ASV-15QC100
廠商: Atmel
文件頁(yè)數(shù): 1/31頁(yè)
文件大小: 0K
描述: IC CPLD 64 MACROCELL LV 100PQFP
標(biāo)準(zhǔn)包裝: 66
系列: ATF15xx
可編程類(lèi)型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時(shí)間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 64
輸入/輸出數(shù): 64
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-PQFP(14x20)
包裝: 托盤(pán)
其它名稱(chēng): ATF1504ASV15QC100
1
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 3.0 to 3.6V Operating Range
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open-collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
– Automatic 5 A Standby for “L” Version
– Pin-controlled 100 A Standby Mode (Typical)
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-free/RoHS Compliant) Package Options
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
Rev. 1409J–PLD–6/05
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