參數(shù)資料
型號: ATF1504ASVL-20QC100
廠商: Atmel
文件頁數(shù): 7/31頁
文件大小: 0K
描述: IC CPLD 20NS 100PQFP
標準包裝: 66
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 20.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 64
輸入/輸出數(shù): 64
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-PQFP(14x20)
包裝: 托盤
其它名稱: ATF1504ASVL20QC10
ATF1504ASVL20QC100
15
ATF1504ASV(L)
1409J–PLD–6/05
Power-down Mode
The ATF1504ASV(L) includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 3 mA. During power down, all output data
and internal logic states are latched internally and held. Therefore, all registered and
combinatorial output data remain valid. Any outputs that were in a High-Z state at the
onset will remain at High-Z. During power down, all input signals except the power-down
pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float
to indeterminate levels, further reducing system power. The power-down mode feature
is enabled in the logic design file or as a fitted or translated s/w option. Designs using
the power-down pin may not use the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
Notes:
1. For slow slew outputs, add t
SSO.
2. Pin or product term.
3. Includes t
RPA for reduced-power bit enabled.
Power Down AC Characteristics
Symbol
Parameter
-15
-20
Units
Min
Max
Min
Max
t
IVDH
Valid I, I/O before PD High
15
20
ns
tGVDH
Valid OE(2) before PD High
15
20
ns
t
CVDH
Valid Clock(2) before PD High
15
20
ns
t
DHIX
I, I/O Don’t Care after PD High
25
30
ns
tDHGX
OE(2) Don’t Care after PD High
25
30
ns
t
DHCX
Clock(2) Don’t Care after PD High
25
30
ns
t
DLIV
PD Low to Valid I, I/O
1
s
tDLGV
PD Low to Valid OE (Pin or Term)
1
s
t
DLCV
PD Low to Valid Clock (Pin or Term)
1
s
t
DLOV
PD Low to Valid Output
1
s
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