- 您現在的位置：買賣IC網 > PDF目錄19641 > ATF1508AS-10AI100 (Atmel)IC CPLD 10NS 100TQFP PDF資料下載
參數資料
| 型號： | ATF1508AS-10AI100 |
| 廠商： | Atmel |
| 文件頁數： | 29/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 10NS 100TQFP |
| 標準包裝： | 90 |
| 系列： | ATF15xx |
| 可編程類型： | 系統內可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內部： | 4.5 V ~ 5.5 V |
| 宏單元數： | 128 |
| 輸入/輸出數： | 80 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508AS10AI100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁
7
ATF1508AS(L)
0784P–PLD–7/05
Speed/Power
Management
The ATF1508AS has several built-in speed and power management features. The
ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power-savings for most applications
running at system speeds below 5 MHz.
To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
I/O Diagram
All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10
mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to
power down the part. The power-down option is selected in the design source file. When
enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down
mode, all internal logic signals are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins,
with Reduced-power Bit turned on. For macrocells in reduced-power mode (Reduced-power
bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which
include the data paths t
LAD, tLAC, tIC, tACL, tACH and tSEXP.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
相關PDF資料 |
PDF描述 |
|---|---|
| GCM02DRKN | CONN EDGECARD 4POS DIP .156 SLD |
| LC4512V-5T176C | IC PLD 512MC 128I/O 5NS 176TQFP |
| VE-BTZ-CY-F1 | CONVERTER MOD DC/DC 2V 20W |
| GMC44DRAI | CONN EDGECARD 88POS R/A .100 SLD |
| ADT7302ARMZ | IC SENSOR TEMP 13BIT DGTL 8MSOP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ATF1508AS-10AL100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10AU100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 5 V ISP CPLD 100 PIN 10NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-10JC84 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 5 V ISP CPLD 100 PIN 10NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-10JI84 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 10NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-10JL84 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
發(fā)布緊急采購，3分鐘左右您將得到回復。