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參數(shù)資料
| 型號： | ATF1508AS-15QI160 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 27/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 15NS 160PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508AS15QI160 |
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5
ATF1508AS(L)
0784P–PLD–7/05
Flip-flop
The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The
flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock,
one of the macrocell product terms can be selected as a clock enable. When the clock enable
function is active and the enable signal (product term) is low, all clock edges are ignored. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-
nous preset (AP) can be a product term or always off.
Extra Feedback
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The 16 foldback terms in each region allows generation of high fan-in sum
terms (up to 21 product terms) with a little additional delay.
3.3V or 5.0V I/O
Operation
The ATF1508AS device has two sets of V
CC pins viz, VCCINT and VCCIO. VCCINT pins must
always be connected to a 5.0V power supply. V
CCINT pins are for input buffers and are “com-
patible” with both 3.3V and 5.0V inputs. V
CCIO pins are for I/O output drives and can be
connected for 3.3/5.0V power supply.
Open-collector
Output Option
This option enables the device output to provide control signals such as an interrupt that can
be asserted by any of the several devices.
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參數(shù)描述 |
|---|---|
| ATF1508AS-7AC100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 5V ISP CPLD 100 PIN 7NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-7AX100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 5V ISP CPLD 100 PIN 7NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-7JC84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 5V ISP CPLD 100 PIN 7NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-7JX84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 7NS IND TEMP GRN RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-7QC100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 7NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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