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參數(shù)資料
| 型號： | ATF1508ASVL-20AI100 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 20NS LOW V LWPWR 100TQFP |
| 標準包裝： | 90 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508ASVL20AI10 ATF1508ASVL20AI100 |
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8
ATF1508ASV(L)
1408H–PLD–7/05
All ATF1508 also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, t
RPA, must be added to the AC
parameters, which include the data paths t
LAD, tLAC, tIC, tACL, tACH and tSEXP.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1508ASV(L) designs are supported by several third-party tools. Automated fitters
allow logic synthesis using a variety of high-level description languages and formats.
Power-up Reset
The ATF1508ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from V
CC crossing VRST, all registers will be ini-
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how V
CC actually rises in the
system, the following conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3.
The clock must remain stable during T
D.
The ATF1508ASV has two options for the hysteresis about the reset level, V
RST, Small
and Large. To ensure a robust operating environment in applications where the device
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on the command line after “file-
name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4.
If V
CC falls below 2.0V, it must shut off completely before the device is turned on
again.
When the Large hysteresis option is active, I
CC is reduced by several hundred micro-
amps as well.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1508ASV(L) fuse
patterns. Once programmed, fuse verify is inhibited. However, User Signature and
device ID remains accessible.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508ASVL-20AU100 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20JC84 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20JI84 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20JU84 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QC100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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