參數(shù)資料
型號(hào)： ATF1508ASVL-20QC100
廠商： Atmel
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 20NS 100PQFP
標(biāo)準(zhǔn)包裝： 66
系列： ATF15xx
可編程類型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 20.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 80
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
包裝： 托盤
其它名稱： ATF1508ASVL20QC10
ATF1508ASVL20QC100
15
ATF1508ASV(L)
1408H–PLD–7/05
JTAG-BST Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port
(TAP) controller in the ATF1508ASV(L). The boundary-scan technique involves the
inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each
component so that signals at component boundaries can be controlled and observed
using scan testing principles. Each input pin and I/O pin has its own Boundary-scan Cell
(BSC) in order to support boundary-scan testing. The ATF1508ASV(L) does not cur-
rently include a Test Reset (TRST) input pin because the TAP controller is automatically
reset at power-up. The six JTAG-BST modes supported include: SAMPLE/PRELOAD,
EXTEST, BYPASS and IDCODE. BST on the ATF1508ASV(L) is implemented using
the Boundary-scan Definition Language (BSDL) described in the JTAG specification
(IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used
to perform BST on the ATF1508ASV(L).
The ATF1508ASV(L) also has the option of using four JTAG-standard I/O pins for in-
system programming (ISP). The ATF1508ASV(L) is programmable through the four
JTAG pins using programming-compatible with the IEEE JTAG Standard 1149.1. Pro-
gramming is performed by using 5V TTL-level programming signals from the JTAG ISP
interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not
needed, then the four JTAG control pins are available as I/O pins.
JTAG Boundary-scan
Cell (BSC) Testing
The ATF1508ASV(L) contains up to 96 I/O pins and four input pins, depending on the
device type and package type selected. Each input pin and I/O pin has its own bound-
ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-
ters and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chained together through
the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin
while the output is directed to the TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration Pins and Macrocells (Except JTAG TAP Pins)
Note:
The ATF1508ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option.
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