參數(shù)資料
型號(hào)： ATF16V8B-15PU
廠商： Atmel
文件頁(yè)數(shù)： 18/26頁(yè)
文件大?。?/td> 0K
描述： IC PLD 15NS 20DIP
標(biāo)準(zhǔn)包裝： 18
系列： 16V8
可編程類型： EE PLD
宏單元數(shù)： 8
輸入電壓： 5V
速度： 15ns
安裝類型： 通孔
封裝/外殼： 20-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 20-PDIP
包裝： 管件
25
7707F–AVR–11/10
AT90USB82/162
6.
System Clock and Clock Options
6.1
Clock Systems and their Distribution
Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 41. The clock systems are detailed below.
Figure 6-1.
Clock Distribution
6.1.1
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
6.1.2
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted.
6.1.3
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
General I/O
Modules
CPU Core
RAM
clk
I/O
AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog Timer
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Crystal
Oscillator
External Clock
System Clock
Prescaler
Clock
Switch
Watchdog
Oscillator
USB
clk
USB (48MHz)
PLL Clock
Prescaler
clk
Pllin (8MHz)
USB PLL
X6
clk
XTAL (2-16 MHz)
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