- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4119 > ATF20V8B-10PI (Atmel)IC PLD 10NS 24DIP PDF資料下載
參數(shù)資料
| 型號： | ATF20V8B-10PI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD 10NS 24DIP |
| 標準包裝： | 15 |
| 系列： | 20V8 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 8 |
| 輸入電壓： | 5V |
| 速度： | 10ns |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 其它名稱： | ATF20V8B10PI |
ATF20V8B(Q)(L)
5
Input Test Waveforms and
Measurement Levels
t
R, tF < 5 ns (10% to 90%)
Output Test Loads
Commercial
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from V
CC crossing
V
RST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the fol-
lowing conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3.
The clock must remain stable during t
PR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
Pin Capacitance
f = 1 MHz, T = 25°C
Typ
Max
Units
Conditions
CIN
58
pF
VIN = 0V
C
OUT
68
pF
V
OUT = 0V
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
相關PDF資料 |
PDF描述 |
|---|---|
| ATF20V8B-10JI | IC PLD 10NS 28PLCC |
| AMM36DTKS | CONN EDGECARD 72POS DIP .156 SLD |
| ASC13DTEN | CONN EDGECARD 26POS .100 EYELET |
| 84953-7 | CONN FPC 7POS 1MM RT ANG SMD |
| 1-1734742-0 | CONN FPC/ZIF 10POS .5MM VERT SMD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATF20V8B-10PU | 功能描述:SPLD - 簡單可編程邏輯器件 15 ns 24 I/O Pins 8 macorcells 8 reg RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF20V8B-10SC | 功能描述:SPLD - 簡單可編程邏輯器件 300 GATE 10NS WAFER - 10NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF20V8B-10SI | 功能描述:SPLD - 簡單可編程邏輯器件 300 GATE EPLD 10NS IND TEMP RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF20V8B-10XC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF20V8B-10XI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
發(fā)布緊急采購，3分鐘左右您將得到回復。