參數(shù)資料
型號: ATF20V8B-15SC
廠商: Atmel
文件頁數(shù): 20/22頁
文件大小: 0K
描述: IC PLD EE 15NS 24-SOIC
標準包裝: 31
系列: 20V8
可編程類型: EE PLD
宏單元數(shù): 8
輸入電壓: 5V
速度: 15ns
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設(shè)備封裝: 24-SOIC W
包裝: 管件
其它名稱: ATF20V8B15SC
ATF20V8B(Q)(L)
7
Note:
1. Only applicable for version 3.4 or lower.
ATF20V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered
mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or com-
binatorial output or I/O, or as an input. For a registered out-
put or I/O, the output is enabled by the OE pin, and the
register is clocked by the CLK pin. Eight product terms are
allocated to the sum term. For a combinatorial output or
I/O, the output enable is controlled by a product term, and
seven product terms are allocated to the sum term. When
the macrocell is configured as an input, the output enable is
permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
20R8
20RP8
20R6
20RP6
20R4
20RP4
Registered Mode Operation
Compiler Mode Selection
Registered
Complex
Simple
Auto Select
ABEL, Atmel-ABEL
P20V8R
P20V8C
P20V8
CUPL
G20V8MS
G20V8MA
G20V8
G20V8A
LOG/iC
GAL20V8_R(1)
GAL20V8_C7(1)
GAL20V8_C8(1)
GAL20V8
OrCAD-PLD
“Registered”
“Complex”
“Simple”
GAL20V8
PLDesigner
P20V8
Tango-PLD
G20V8
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