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參數(shù)資料
| 型號(hào)： | ATF22LV10C-15SC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD EE 15NS 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 系列： | 22V10 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 10 |
| 輸入電壓： | 3.3V |
| 速度： | 15ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 其它名稱： | ATF22LV10C15SC |
6
0780M–PLD–7/10
Atmel ATF22LV10C
3.7
Power-up Reset
The registers in the Atmel ATF22LV10C are designed to reset during power-up. At a point delayed slightly from
V
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the following conditions are required:
1.
The V
CC rise must be monotonic and start below 0.7V
2.
The clock must remain stable during T
PR
3.
After T
PR, all input and feedback setup times must be met before driving the clock pin high
3.8
Preload of Register Outputs
The ATF22LV10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
4.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
6.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware &
Software Support for information on software/programming.
Table 6-1.
Programming/Erasing
7.
Input and I/O Pin-keeper
All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs
and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by
TTL-compatible drivers (see Input and I/O diagrams on page 7).
Parameter
Description
Typ
Max
Units
T
PR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
2.5
3.0
V
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參數(shù)描述 |
|---|---|
| ATF22LV10C-15SI | 功能描述:SPLD - 簡單可編程邏輯器件 EEPLD 500GATE STDPWR 3.3V 15NS IND TEMP RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10C-15XC | 功能描述:SPLD - 簡單可編程邏輯器件 500 GATE STANDARD POWER 3.3V - 15NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10C-15XI | 功能描述:SPLD - 簡單可編程邏輯器件 ASICS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CQZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-performance Electrically Erasable Programmable Logic Device |
| ATF22LV10CQZ-30JC | 功能描述:SPLD - 簡單可編程邏輯器件 500 GT 3.3-5V SPLY ZERO/QRTR PWR-30NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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