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參數(shù)資料
| 型號(hào)： | ATF22V10B-15PI |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | High- Performance EE PLD |
| 中文描述： | FLASH PLD, 15 ns, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 294K |
| 代理商： | ATF22V10B-15PI |
ATF22LV10C(Q)Z
5
Input Test Waveforms and
Measurement Levels
Output Test Loads
Note:
Similar competitors devices are specified with slightly
different loads. These load differences may affect output
signals
’
delay and slew rate. Atmel devices are tested
with sufficient margins to meet compatible device specifi-
cation conditions.
Notes:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF22LV10CZ/CQZ are designed to
reset during power-up. At a point delayed slightly from V
CC
crossing V
RST
, all registers will be reset to the low state.
The output state will depend on the polarity of the buffer.
This feature is critical for state machine initialization.
However, due to the asynchronous nature of reset and the
uncertainty of how V
CC
actually rises in the system, the
following conditions are required:
1.
The V
CC
rise must be monotonic and start
below 0.7V.
2.
The clock must remain stable during T
PR
.
3.
After T
PR
, all input and feedback setup times must
be met before driving the clock pin high.
Preload of Register Outputs
The ATF22LV10CZ/CQZ
’
s registers are provided with cir-
cuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can
be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22LV10CZ/CQZ fuse patterns. Once pro-
grammed, fuse verify and preload are inhibited. However,
the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard
PLD programmers. See CMOS PLD Programming
Hardware & Software Support for information on software/
programming.
Pin Capacitance
f = 1 MHz, T = 25
°
C
(1)
Typ
Max
Units
Conditions
C
IN
5
8
pF
V
IN
= 0V
C
I/O
6
8
pF
V
OUT
= 0V
Parameter
Description
Typ
Max
Units
T
PR
Power-up
Reset Time
600
1000
ns
V
RST
Power-up
Reset Voltage
2.3
2.7
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATF22V10B-15SC | High- Performance EE PLD |
| ATF22V10B-15SI | High- Performance EE PLD |
| ATF22V10B-15XC | High- Performance EE PLD |
| ATF22V10B-15XI | High- Performance EE PLD |
| ATF22V10B-25JC | High- Performance EE PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF22V10B-15SC | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 ASICS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22V10B-15SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 500 Gate RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22V10B-15XC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF22V10B-15XI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF22V10B25GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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