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參數(shù)資料
| 型號： | ATF2500C-20PU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD EE 20NS 40DIP |
| 標準包裝： | 100 |
| 系列： | ATF2500C(L) |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 24 |
| 輸入/輸出數(shù)： | 24 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 608 (CN2011-ZH PDF) |
3
0777K–PLD–1/24/08
ATF2500C
3.
Using the ATF2500C Family’s Many Advanced Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
Fully Connected Logic Array – Each array input is always available to every product term.
This makes logic placement a breeze.
Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also
easily created. These options allow more efficient product term usage.
Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed
its input (D/T2) directly back to the logic array. This provides further logic expansion capability
without using precious pin resources.
Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has
a dedicated clock product term. This removes the constraint that all registers use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48.
Each register has its own clock and reset terms, as well as its own sum term.
Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated
input path. Each of the 48 registers has its own feedback term into the array as well. These
features, combined with individual product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into
a single term. This provides a fan in of up to 12 product terms per sum term with no speed
penalty.
Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
User Row (64 bits) – Use to store information such as unit history.
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參數(shù)描述 |
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| ATF2500CL-20JC | 功能描述:IC CPLD 24 MACRO 20NS 40PLCC 制造商:microchip technology 系列:ATF2500C（L） 包裝:管件 零件狀態(tài):停產(chǎn) 可編程類型:系統(tǒng)內(nèi)可編程 延遲時間 tpd（1）最大值:20.0ns 電源電壓 - 內(nèi)部:4.75 V ~ 5.25 V 宏單元數(shù):24 I/O 數(shù):24 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:44-LCC（J 形引線） 供應(yīng)商器件封裝:44-PLCC（16.58x16.58） 基本零件編號:ATF2500 標準包裝:27 |
| ATF25100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | N-CHANNEL | 50MA I(DSS) | CHIP |
| ATF25170 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | N-CHANNEL | 50MA I(DSS) | MICRO-XVAR |
| ATF-25170 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:0.5-10 GHz Low Noise Gallium Arsenide FET |
| ATF25570 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | JFET | N-CHANNEL | 50MA I(DSS) | MICRO-XVAR |
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